The present disclosure relates generally to integrated circuit device design, and more specifically, to a layout for a field effect transistor (FET) device with a multiple fins that are tapered and have merged regions.
Multi-fingered field effect transistors (FETs) are widely used in various integrated circuit applications. Multi-finger transistor layouts are widely used in CMOS circuit designs. Compared with single-finger transistor layout, its main features include effectiveness in reducing circuit physical size, reducing gate resistance (and thus improve the RF performance of the FET), and improving device matching. One FinFET architecture employs the ‘merging’ of source/drain regions of fins to arrive at planar-like contact rules/processes. This merged region adds to gate-to-drain (and source) capacitance, which increases circuit delay and power, both elements highly undesirable. This disclosure teaches a structure and method to reduce this deleterious capacitance in a merged Fin architecture.